This application claims priority to Korean Patent Application No. 2004-52316, filed on Jul. 6, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to clock signal generators, and more particularly, to a clock switching apparatus that switches between clock signals without generating a glitch.
2. Description of the Related Art
Digital electronic systems often use a clock signal to synchronize and control operations of various circuits (e.g., logic gates, flip-flops, latches, etc.). In many digital electronic systems including a microprocessor, there exist multiple clock sources. Mechanisms for switching between the clock sources are needed.
FIG. 1 is a block diagram of a conventional clock selection circuit using a multiplexer 100. Referring to FIG. 1, the multiplexer 100 receives two clock signals, including a fast clock signal CLOCK_FAST and a slow clock signal CLOCK_SLOW. The multiplexer 100 switches between the fast clock signal CLOCK_FAST and the slow clock signal CLOCK_SLOW in response to a selection signal SELECT to generate an output clock signal CLOCK_OUT.
For example, when the selection signal SELECT is logic high, the slow clock signal CLOCK_SLOW is output as the output clock signal CLOCK_OUT. Alternatively, when the selection signal SELECT is logic low, the fast clock signal CLOCK_FAST is output as the output clock signal CLOCK_OUT.
FIG. 2 shows a timing diagram of the signals SELECT, CLOCK_FAST, CLOCK_SLOW, and CLOCK_OUT during operation of the clock selection circuit of FIG. 1. Referring to FIG. 2, when the selection signal SELECT is logic high, the CLOCK_SLOW signal is output as the output clock signal CLOCK_OUT. In the example of FIG. 2, the logic level of the SELECT signal transitions from logic high to logic low when the CLOCK_SLOW signal is logic high and the CLOCK_FAST signal is logic low. At this time, a shortened pulse 210 (i.e., a glitch) is generated in the output clock signal CLOCK_OUT.
Subsequently, in response to the logic low level of the SELECT signal, the fast clock signal CLOCK_FAST is output as the output clock signal CLOCK_OUT. Thereafter, the logic level of the SELECT signal transitions from logic low to logic high when the fast clock signal CLOCK_FAST is logic low and the slow clock signal CLOCK_SLOW is logic high. At this time, another shortened pulse 220 (i.e., another glitch) is generated in the output clock signal CLOCK_OUT.
Generally, a glitch causes errors during execution of a microprocessor or other system components because the glitch may erratically clock flip-flops, latches, etc. Therefore, prevention of glitches is desired. U.S. Pat. Nos. 6,559,679 and 6,600,345 disclose mechanisms for preventing glitches. The circuits disclosed in U.S. Pat. Nos. 6,559,679 and 6,600,345 are illustrated in FIGS. 3 and 4, respectively.
In a glitch-free clock multiplexer circuit of FIG. 3 from U.S. Pat. No. 6,559,679, occurrence of glitches is prevented by holding an output clock signal CLOCK_OUT while transitions of an A clock signal CLOCK_A and a B clock signal CLOCK_B are being counted. However, the glitch-free clock multiplexer circuit of FIG. 3 is suitable for a case where a difference between frequencies of the A and B clock signals CLOCK_A and CLOCK_B is not significant and may be determined.
When the difference between the frequencies of the A and B clock signals CLOCK_A and CLOCK_B cannot be determined, a transition interval between clock switching cannot be determined, thereby causing a problem in producing a logic state transition. When the difference between the frequencies of the A and B clock signals CLOCK_A and CLOCK_B is significant, a delay interval between switching increases due to an influence of one of the CLOCK_A and CLOCK_B signals with the lower frequency. Such an increase in delay interval results in a long delay between when the clock selection signal SEL_CLOCK transits and when the output clock signal CLOCK_OUT is switched.
A glitch-free clock selection switch of FIG. 4 from U.S. Pat. No. 6,600,345 needs synchronization logic to produce enable signals EN1 and EN2 used upon clock switching between first and second clock signals CLOCK_1 and CLOCK_2. The glitch-free clock selection switch of FIG. 4 prevents the occurrence of glitches in an output clock signal CLOCK_OUT by latching a slow clock signal and a fast clock signal twice each.
Unfortunately, when the difference between frequencies of the first and second clock signals CLOCK_1 and CLOCK_2 is significant in FIG. 4, a delay interval between switching increases due to an influence of one of the clock signals CLOCK_1 and CLOCK_2 with the lower frequency. Such an increase in delay interval results in a long delay between when the enable signals EN1 and EN2 transit and when the output clock signal CLOCK_OUT is switched.
Thus, a mechanism is desired for switching between clock signals with minimized clock switching interval regardless of a difference between frequencies of the clocks.